Senior DFT Engineer

We’re looking for a Senior DFT Engineer with expertise in architecting DFT solutions for SOC (MBIST, SCAN, ATPG, LBIST and more).

Developing all the necessary HW / FW / SW for the different modules, verify/validate the design, working closely with synthesis, STA, PD and DFT teams to meet all functional requirements, performance, power and area goals, functional and diagnostics test coverage.

The responsibility includes debug and analyze coverage and yield loss.

Required to the have ability to lead/manage a team, with active technical interaction with engineering teams.

About Us
Our group is responsible for the development of NeuReality next generation SoC for AI Compute. The development starts from product definition through architecture, design, verification and up to implementation.
The complex SoC is a high-performance device running AI compute for vision and audio processing, with technologies from multi-disciplines.


  • 5+ years of hands-on experience with DFT and test flow with commercial EDA tools (Synopsys, Mentor) for large and complex SoCs.
  • Strong fundamental knowledge of DFT techniques include JTAG, ATPG, test pattern translation, yield learning, logic diagnosis, Scan compression, IEEE 1500 Std. and MBIST, LBIST.
  • At least 8 years of experience in the ASIC/SoC industry
  • BSC/MSC in Electrical/Computer engineering from research universities.
  • Leadership capabilities.
  • Caesarea Main Office: 14 Tarshish Street, Industrial Park Caesarea 3079559, Israel
    Tel Aviv: BE ALL Alon: Igal Alon 94, Alon 1, Tel Aviv, Israel
  • +972-54-3200157
*Required Fields